
2008 Microchip Technology Inc.
DS39626E-page 21
PIC18F2525/2620/4525/4620
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
RD
AN5
825
25
I/O
I
ST
TTL
Analog
Digital I/O.
Read control for Parallel Slave Port
(see also WR and CS pins).
Analog input 5.
RE1/WR/AN6
RE1
WR
AN6
926
26
I/O
I
ST
TTL
Analog
Digital I/O.
Write control for Parallel Slave Port
(see CS and RD pins).
Analog input 6.
RE2/CS/AN7
RE2
CS
AN7
10
27
I/O
I
ST
TTL
Analog
Digital I/O.
Chip select control for Parallel Slave Port
(see related RD and WR).
Analog input 7.
RE3
—
See MCLR/VPP/RE3 pin.
VSS
12, 31 6, 30,
31
6, 29
P
—
Ground reference for logic and I/O pins.
VDD
11, 32
7, 8,
28, 29
7, 28
P
—
Positive supply for logic and I/O pins.
NC
—
13
12, 13,
33, 34
—
No connect.
TABLE 1-3:
PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
PDIP
QFN
TQFP
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I
= Input
O
= Output
P
= Power
Note 1:
Default assignment for CCP2 when the CCP2MX Configuration bit is set.
2:
Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
3:
For the QFN package, it is recommended that the bottom pad be connected to VSS.